QoS · Topic 2 of 3

CRS Priority Configuration and Switch Chip Rate Limits

Understand how a CRS switch chip classifies priority into hardware queues, and how ingress and egress rate limits cap a switch port at wire speed.

4 min

In a nutshell

A CRS switch chip classifies, queues and schedules in hardware.
QoS is configured under the /interface ethernet switch menus.
The chip takes priority from the PCP, from a port default, or from a rule.

What it is

A CRS switch chip applies QoS in hardware, so priority and rate limits work at wire speed with no CPU load.

The chip reads the priority of each frame, places it in one of a small number of hardware queues, and sends frames from the queues in a fixed order. It can also limit the rate on a port.

The settings live under the /interface ethernet switch menus, and the exact menus depend on the chip family.

How it works

The chip makes three decisions: how to classify, which queue to use, and how to serve the queues.

Classification

First the chip decides what priority a frame has.

It can take the PCP bits from a VLAN tag.
It can use a default priority set on the ingress port, for frames without a tag, on chips that support it.
It can use a switch rule that matches the frame and sets a priority.

Each port can be set to trust the incoming value, or to override it. This is the same trust decision you make on a bridge, and it has the same risk if user ports are trusted.

Queue mapping and scheduling

The priority is mapped to a hardware queue.

A chip has a limited number of queues, often fewer than the eight priority values. Several priority values can share one queue. The scheduler then serves the queues, usually giving higher queues strict preference, or a weighted share.

The effect is visible only when a port is congested. If the egress port has spare capacity, all queues drain at once.

Priority on egress

Some chips can also re-mark the priority in the tag on the way out.

This helps at a boundary, where the next network may use different values for the same traffic class. Support depends on the chip family, so check the documentation.

Switch rules for priority

A switch rule can match traffic and assign a new priority.

/interface ethernet switch rule add ports=ether2 mac-protocol=ip new-vlan-priority=5

This marks IPv4 frames from ether2 with priority 5 in the chip, with no CPU involved. The rule table is small, so use rules for important cases only. The rule parameters differ between chip families, so check the documentation of the device.

Exam tip

Do the classification and marking in the chip wherever you can. A bridge filter would force the traffic through the CPU.

Bandwidth limiting in the chip

The chip can limit how fast traffic enters or leaves a port.

/interface ethernet switch port set ether3 ingress-rate=10M egress-rate=10M

Setting	Effect
`ingress-rate`	Limits traffic received on the port
`egress-rate`	Limits traffic sent out of the port

Each setting holds the port to the rate you give. How the chip treats the excess frames depends on the family.

Both run in hardware, so they do not slow the switch. They are simple limits on the whole port, and cannot tell one customer from another behind the same port.

Limits compared with bridge queues

Aspect	Chip rate limit	Queues on the CPU
Speed	Wire speed	Limited by the CPU
Flexibility	A single rate per port	Rules by address, protocol and mark
Fairness between hosts	None	Possible, with queue types

Use the chip for a plain port limit, and queues when you need rules by host or by traffic type.

Checking

/interface ethernet switch port print
/interface ethernet switch rule print

Look at the port settings and the rules, and then check the effect with a speed test on the limited port.

What to remember for the exam

Seven facts cover most questions on this topic.

A CRS switch chip classifies, queues and schedules in hardware.
QoS is configured under the /interface ethernet switch menus.
The chip takes priority from the PCP, from a port default, or from a rule.
Several priority values can share one hardware queue.
Queues only matter when the egress port is congested.
ingress-rate and egress-rate limit a port at wire speed.
A port limit cannot separate hosts behind the port.

Watch out

Chip level QoS names and parameters differ between CRS families. Read the documentation for your exact model before you copy a configuration.

Common mistakes

These four mistakes appear often.

Using the CPU for work the chip can do. A bridge filter or queue slows a CRS that could switch in hardware.

Expecting a rate limit to be fair. A port limit is one shared rate, with no per host share.

Trusting the wrong ports. Trust the PCP only on links to devices you control.

Testing on an idle link. Queues show their effect only under congestion.

Check yourself

Work through these three questions.

Where does the CRS chip take the priority of a frame from?
From the PCP bits of the tag, from a default priority on the port, or from a switch rule.
What do ingress-rate and egress-rate do?
They limit the traffic received on, or sent out of, a switch port, at wire speed.
When does the queue mapping have an effect?
Only when the egress port is congested.

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